# UAVCAN V0 on CAN3 peripheral, STM32F7 **URL:** \ **Category:** Libcanard\ **Created:** [March 2, 2021, 7:30pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144 "2021-03-02T19:30:55Z")\ **Posts on this page:** 9\ **Page:** 1
**Author:** ![EFalcione](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/efalcione/32/895_2.png) [@EFalcione](https://forum.opencyphal.org/u/EFalcione)\ **Post date:** [March 2, 2021, 7:30pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/1 "2021-03-02T19:30:55Z")
I am working on an existing project that uses UAVCAN V0 Libcanard on an STM32F7. My understanding is that this microcontroller has three CAN outputs. CAN1 and 2 are multiplexed on the same hardware, and CAN3 has its own hardware inside the chip. I’d like to use CAN3 for sending/receiving UAVCAN messages. In the drivers folder on the Libuavcan git repo, the canard\_stm32.c and .h files and the \_internal\_bxcan.h file appear to only contain code for using CAN1 and CAN2. Does any code exist for setting up and using CAN3? > **[UAVCAN/libcanard](https://github.com/UAVCAN/libcanard/tree/8ee343c4edae0e0e4e1c040852aa3d8430f7bf76/drivers/stm32)** > > A compact implementation of the UAVCAN/CAN protocol in C for high-integrity real-time embedded systems - UAVCAN/libcanard ---
**Author:** ![pavel.kirienko](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/pavel.kirienko/32/9_2.png) [@pavel.kirienko](https://forum.opencyphal.org/u/pavel.kirienko)\ **Post date:** [March 2, 2021, 7:38pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/2 "2021-03-02T19:38:17Z")
> [@EFalcione](#): > > Does any code exist for setting up and using CAN3? I am not aware of any but you better search through GitHub to be sure. If you don’t find anything relevant there, you will need to modify the driver yourself to add support for CAN3. ---
**Author:** ![EFalcione](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/efalcione/32/895_2.png) [@EFalcione](https://forum.opencyphal.org/u/EFalcione)\ **Post date:** [March 4, 2021, 9:45pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/3 "2021-03-04T21:45:24Z")
Unfortunately I don’t see anything pre-existing on git. To the \_internal\_bxcan.h file I added: #define CANARD\_STM32\_CAN3 ((volatile CanardSTM32CANType\*)0x40003400U) //Memory location of CAN3 config register from stm32f767xx.h. I added another build config macro to canard\_stm32.h for using CAN3 and set it to 1. The build config macros for CAN1 and 2 are set to zero. I adjusted the #defines at the top of canard\_stm32.c to look like this: #if CANARD\_STM32\_USE\_CAN3 #define BXCAN CANARD\_STM32\_CAN3 #elif CANARD\_STM32\_USE\_CAN2 #define BXCAN CANARD\_STM32\_CAN2 #elif CANARD\_STM32\_USE\_CAN1 #define BXCAN CANARD\_STM32\_CAN1 #endif However, the canardSTM32Init function errors out at the first instance of: if(!waitMSRINAKBitStateChange(BXCAN, true)) It appears the value of the MCR register at this point is incorrect. I expect MCR to end in 01 (not sleep mode, request init), but instead it ends in 10 (sleep mode, not requesting init). The lines immediately preceeding the if statement are: BXCAN-\>MCR &= ~CANARD\_STM32\_CAN\_MCR\_SLEEP; // Exit sleep mode BXCAN-\>MCR |= CANARD\_STM32\_CAN\_MCR\_INRQ; // Request init I expect these lines to change the last two bits of MCR from 10 to 01, but these lines have no effect on the value of MCR. Any thoughts on why this might be? I don’t think the MCR register is locked somehow. ---
**Author:** ![pavel.kirienko](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/pavel.kirienko/32/9_2.png) [@pavel.kirienko](https://forum.opencyphal.org/u/pavel.kirienko)\ **Post date:** [March 4, 2021, 9:50pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/4 "2021-03-04T21:50:00Z")
> [@EFalcione](#): > > Any thoughts on why this might be? Make sure you enabled the clock for the bxCAN macrocell. Depending on its configuration, you may also need to initialize CAN1 and/or CAN2, because in other STM32’s CAN2 cannot be initialized unless CAN1 is also active. Be sure to also set up the GPIO AF registers properly otherwise you will be getting INAK timeouts during initialization, although right now this is less relevant. If you posted your code here somebody might be able to help. ---
**Author:** ![EFalcione](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/efalcione/32/895_2.png) [@EFalcione](https://forum.opencyphal.org/u/EFalcione)\ **Post date:** [March 9, 2021, 5:10pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/5 "2021-03-09T17:10:25Z")
Ah, once I enabled the CAN3 timer it works great! Thanks for your advice. ---
**Author:** ![EFalcione](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/efalcione/32/895_2.png) [@EFalcione](https://forum.opencyphal.org/u/EFalcione)\ **Post date:** [May 6, 2021, 6:12pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/6 "2021-05-06T18:12:00Z")
Is there any interest in adding support for CAN3 to the code on the UAVCANv0 git repo? (I know v0 is legacy, and perhaps not being updated anymore.) I’m happy to contribute my code. ---
**Author:** ![pavel.kirienko](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/pavel.kirienko/32/9_2.png) [@pavel.kirienko](https://forum.opencyphal.org/u/pavel.kirienko)\ **Post date:** [May 6, 2021, 6:24pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/7 "2021-05-06T18:24:09Z")
Sure. It would be even better to port your code to the new bxCAN driver in the v1 branch. ---
**Author:** ![EFalcione](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/efalcione/32/895_2.png) [@EFalcione](https://forum.opencyphal.org/u/EFalcione)\ **Post date:** [May 11, 2021, 4:28pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/8 "2021-05-11T16:28:38Z")
Thanks. Is this done via pull request? ---
**Author:** ![pavel.kirienko](https://forum.opencyphal.org/user_avatar/forum.opencyphal.org/pavel.kirienko/32/9_2.png) [@pavel.kirienko](https://forum.opencyphal.org/u/pavel.kirienko)\ **Post date:** [May 11, 2021, 4:29pm UTC](https://forum.opencyphal.org/t/uavcan-v0-on-can3-peripheral-stm32f7/1144/9 "2021-05-11T16:29:53Z")
Yes.